1. Technical Field
The present invention relates to a method of fabricating a semiconductor device and a semiconductor device fabricated thereby, and more particularly, to a method of fabricating a flash memory device and a flash memory device fabricated thereby.
2. Discussion of the Related Art
A flash memory device is a non-volatile memory device capable of erasing or programming information electrically, and is widely used as a memory device of electronic appliances such as computers, digital cameras, or the like. The flash memory device has two gates, that is, a floating gate used as a charge storage layer, and a control gate for controlling input and output signals. Further, in accordance with the structures of the floating gate and the control gate, it can be classified as a stack gate flash memory device or a split gate flash memory device.
The fabrication of a highly-integrated semiconductor device having a stack structure involves a number of photolithography processes. However, with the increased demand in high integration of semiconductor devices, the photolithography process requires solutions to solve the limitation of resolution and interlayer misalignment. For example, in the process of forming a floating gate of the flash memory device, the floating gate needs to be exactly aligned to the active region of the semiconductor substrate. However, as described above, it is difficult to form a floating gate of a desired shape due to the limitation of the photolithography process, and furthermore, there may occur a misalignment with an active region under the floating gate. Because of this, there occurs a problem of deteriorating the cell characteristics in each cell of the flash memory device, i.e., a length of a channel under the floating gate is short, or the channel is not generated at all. As efforts to overcome the problems, various methods have been introduced to align the floating gate with the active region of the semiconductor substrate.
A method of fabricating a conventional flash memory device to form a self-aligned floating gate on the active region of the semiconductor substrate is disclosed in U.S. Pat. No. 6,627,942.
FIG. 1 is a sectional view showing a method of fabricating a conventional flash memory device disclosed in the above U.S. Pat. No. 6,627,942.
Referring to FIG. 1, an isolation layer 104 confining an active region 102 is formed in a semiconductor substrate 100. The isolation layer 104 is formed by a shallow trench isolation (STI) process, and has a protrusion being higher than the surface of the semiconductor substrate 100 to have a step_difference with the surface of the semiconductor substrate 100. Then, a gate oxide layer 106 is formed on the active region 102. After forming a polysilicon layer on the entire surface of the semiconductor substrate 100 having the gate oxide layer 106, a chemical mechanical polishing (CMP) process is performed. As a result, a self-aligned polysilicon layer pattern 108 is formed on the active region 102. The polysilicon layer pattern 108 is used as a floating gate of the flash memory device.
As described above, in the method of fabricating a conventional flash memory device, a self-aligned floating gate can be formed in the active region. However, a problem may be caused in a subsequent process of forming an oxide layer in the method described as above. For example, in the method of fabricating a split gate flash memory device, a polysilicon oxide layer is formed on the polysilicon layer pattern 108 by a thermal oxidation process after forming the polysilicon layer pattern 108. During the process, an interface B between the isolation layer 104 and the polysilicon layer pattern 108 can be used as a diffusion path of oxygen. As a result, there may occur a smile effect in which a thickness of the gate oxide layer 106 adjacent to the interface B is thick. By the smile effect, since the thickness of the gate oxide layer 106 is non-uniform, the electrical characteristics of each cell of the split gate flash memory device may be deteriorated.